Linear regulators are widely deployed for providing a regulated output voltage based on an inputted reference voltage, such as a reference voltage that might be provided by a bandgap reference. A simplified example of a conventional linear regulator is depicted in FIG. 1.
As shown in FIG. 1, linear regulator 10 includes op-amp 1 connected in a linear feedback loop based on voltage reference Vref. Op-amp 1 drives the gate of NMOS transistor 2, which is connected in series with a resistor-capacitor network of load resistor 3 (RL) and load capacitor 4 (CL). Because of the linear feedback loop in which op-amp 1 is connected, output voltage 5 is equal to the reference voltage, i.e., Vo=Vref.
The FIG. 1 linear regulator 10 effectively attenuates low frequencies in the power supply, and at low frequencies the relationship of Vo=Vref is accurate. However, for higher frequencies in the power supply, the effect of parasitic capacitance becomes more pronounced. Specifically, the parasitic capacitance Cds between source and drain of NMOS transistor 2 affects the ability of the linear regulator 10 to reject high frequencies in the power supply. In particular, at high frequencies, the ability of linear regulator 10 to achieve high power supply rejection is determined by the ratio of Cds to CL.
As a consequence, for good power supply rejection at high frequencies, it is preferable that CL be as large as possible. However, large values for CL are not easy to fabricate, and in addition large values of CL tend to destabilize the linear feedback loop.
Thus, conventional linear regulators suffer from an inability to achieve good rejection of high frequency components of the power supply.